1. Field of the Invention
The invention relates generally to the testing of electronic circuits, and more particularly to systems and methods for using test circuitry (some components of which are built into the device under test) to identify the existence of circuit defects and to provide data to localize the defects in the device under test, including the means for data transfer through a limited number of I/O ports.
2. Related Art
Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Finally, after the device is manufactured, it may be necessary to test the device at normal operating speeds to ensure that it continues to operate properly during normal usage.
One way to test for defects in a logic circuit is a deterministic approach. In a deterministic method, each possible input pattern is applied at the inputs of the logic circuit, with each possible set of state values in the circuit. The output pattern generated by each set of inputs and state values is then compared with the expected output pattern to determine whether the logic circuit operated properly. If the number of possible input patterns and number of states is large, however, the cost of deterministic testing of all the combinations is generally too high for this methodology to be practical. An alternative method of testing that has a lower cost is therefore desirable.
One alternative is a non-deterministic approach in which pseudorandom input test patterns are applied to the inputs of the logic circuit. The outputs of the logic circuit are then compared to the outputs generated in response to the same pseudorandom input test patterns by a logic circuit that is known to operate properly. If the outputs are the same, there is a high probability that the logic circuit being tested also operates properly. The more input test patterns that are applied to the logic circuits, and the more random the input test patterns, the greater the probability that the logic circuit under test will operate properly in response to any given input pattern. This non-deterministic testing approach is typically easier and less expensive to implement than a deterministic approach.
Deterministic testing approaches can be implemented using design-for-test (DFT) methodologies. DFT methodologies impact the actual designs of the circuits that are to be tested. DFT methodologies may use various approaches, and may incorporate all of the test circuitry, or only parts of the circuitry into the device under test. Logic built-in self-test (LBIST) methodologies in particular involve incorporating essentially all of the test circuitry components into the design of the device to be tested. Other methodologies (e.g., OpMISR and MOXIE) incorporate a portion of the test circuitry components into the device under test.
In a typical OPMISR or MOXIE system, test circuitry within a device under test includes a plurality of scan chains interposed between levels of the functional logic of the device. Typically, pseudorandom patterns of bits are generated and stored in the scan chains. This may be referred to as scanning the data into the scan chains. After a pseudorandom bit pattern is scanned into a scan chain, the data is propagated through the functional logic (at some test rate) to a subsequent scan chain. The data is then scanned out of the subsequent scan chain and compressed to reduce storage and bandwidth requirements (e.g., through the use of a multiple input signature register.) This test loop is typically repeated many times (e.g., 10,000 iterations,) with the results of each test loop being combined in some manner with the results of the previous test loops. After all of the scheduled test loops have been completed, the final result is compared to a final result generated by a device that is known to operate properly operated in an identical test (using identical input data processed at the same test rate.) Based upon this comparison, it is determined whether the device under test operated properly.
This conventional configuration has some drawbacks, however. Since the number of output ports is limited (e.g., using the input ports for output), the output bandwidth needs to be reduced and is done so by combining the test output bits. This compression of the functional logic output results in a loss of some of the information content.
For example, four functional blocks within a device under test each produce a 32 bit wide signature by means of a multiple input signature register (MISR). (Assume there are 32 output ports available.) Each of the four MISRs can be compacted from 32 bits to 8 bits and concatenated so that a total of 32 bits is output. In another example, the four MISR signatures are OR'd together, reducing the number of bits from to 32. Consequently, data errors that propagated into the signature value in a particular MISR can no longer be identified when combined with other MISR results. In another example, only 8 ports are available, and, instead of concatenation, the 4 compacted MISR signatures are combined and compacted into an 8-bit signature. Again, any error localization information originally preserved within the MISR signatures would then be corrupted.
The lost information can be valuable in determining the root cause of the malfunction so that the defects can be eliminated or their effect mitigated. It would therefore be desirable to provide systems and methods able to test the circuitry and provide results, without having to resort to data compression.